The present invention relates generally to methods for forming integrated electronic circuits, and in particular, to methods for forming MOS circuits using plural overlapping layers of different semiconductor materials.
Silicon integrated circuits “IC's” are ubiquitous in modern electronics. These integrated electronic circuits, which contain up to millions of transistors, can be formed simultaneously by a series of process steps using masks containing millions of features. Silicon IC technology has led to an explosion of such electronic devices as computers, handheld telephones, portable music and movie players.
Ever more sophisticated and powerful appliances are enabled by increasing the density and speed of silicon IC technology, as well as by decreasing the cost. Continuing to increase the speed and density of integrated circuits is becoming an ever greater challenge. Much of the last twenty years of silicon scaling has proceeded by reducing the lateral dimensions on the masks and proportionally reducing the thickness of the various layers of the circuit. However, the current gate oxide layer in a conventional metal-oxide-silicon (“MOS”) transistor is no more than a few atoms thick, and the lateral dimensions which must be patterned by lithography are now less than the wavelength of the light used to illuminate them. Further scaling is proving to be increasingly difficult, and alternate approaches to increasing the density and speed of integrated electronic circuits are desired.
One technique of increasing speed in modern transistors is to improve the mobility of carriers by introducing strain. Strain can be introduced by a variety of processing techniques, such as the deposition of dielectric layers with high intrinsic strain, or the growth of silicon layers on a template material which has a different lattice constant, such as silicon-germanium. By judicious choice of materials, a particular strain state can be built into a transistor and can enhance the mobility of carriers therein. An alternative approach uses different crystal orientations to optimize the mobility of holes and electrons separately. By bonding silicon islands of one crystal orientation to a silicon wafer of a different orientation, the mobility of holes can be enhanced without adversely affecting the mobility of electrons.
Each of these examples continues to use silicon as the semiconductor in which the transistors are formed. Silicon has been the preferred material for integrated electronic circuits, primarily because it has a high-quality native oxide. However, the advent of high-dielectric constant (“high-K”) gate insulators provides a new opportunity to consider semiconductors other than silicon for future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs). For example, germanium is a semiconductor in the same chemical family as silicon. The process chemistry of germanium is fully compatible with silicon and is already used today as a dilute additive in silicon processes to enhance transistor performance.
Considerable efforts have been made to grow germanium transistor material on silicon. However, the growth of pure germanium on a silicon substrate is difficult, due to the large lattice mismatch (4%) between the silicon and germanium crystals. Many techniques have been proposed by others to grow pure germanium on silicon, but they have produced highly defective material which is not of electronic interest.